How Solid-State Drives (SSDs) and Flash Memory Store Data Without Power

The Non-Volatile Paradox: Trapping Electrons Without a Wire

When your computer is running, its active working memory lives in Dynamic Random Access Memory (DRAM). Every bit in a DRAM chip is stored as an electrical charge inside a microscopic capacitor wired directly to the source-drain channel of an access transistor (1T1C). That direct electrical connection makes DRAM extraordinarily fast—reading or writing a row takes roughly 14 nanoseconds—but it creates an inescapable vulnerability: wherever a wire or semiconductor junction exists for charge to enter in nanoseconds, charge will also leak out in milliseconds. Turn off the power, and within 64 milliseconds every DRAM capacitor drains to ground and your working memory vanishes.

For decades, the only practical way to preserve gigabytes of data without power was to abandon electronics altogether and store bits magnetically on spinning platters coated with cobalt-platinum alloys (Hard Disk Drives). Magnetic domains do not leak when power is cut, but reading them requires swinging a physical actuator arm across a platter spinning at 7,200 RPM—imposing a mechanical seek latency of 5 to 10 milliseconds, nearly a million times slower than DRAM.

A Solid-State Drive (SSD) bridges this divide through NAND Flash Memory, a solid-state technology that retains trillions of bits for years without power while reading data in tens of microseconds with zero moving parts.

To understand how flash memory works, you must first appreciate the paradox at its core:

1. To hold an electric charge for years without a battery, the storage element must be completely surrounded by a high-grade electrical insulator—with no wire, contact, or transistor junction connected to it.
2. To write or erase data, electrons must somehow pass into and out of that completely insulated island on demand, millions of times, without destroying the insulator.

Classical physics says you cannot have both: either a conductor is wired to a circuit (and leaks), or it is insulated (and cannot be written). Flash memory resolves this paradox by abandoning classical conduction during writes and relying on quantum mechanical tunneling.

1. The Flash Cell: How Trapped Electrons Shift a Transistor's Threshold Voltage

Every flash memory cell is a modified Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

In an ordinary n-channel MOSFET, applying a positive voltage to the Control Gate creates a vertical electric field across a thin insulating oxide layer. Once that gate voltage exceeds a characteristic minimum called the Threshold Voltage (V_th), the electric field pulls free electrons to the surface of the underlying p-type silicon substrate, forming a conductive inversion channel that allows current to flow from the Source to the Drain.

In 1967, Bell Labs physicists Dawon Kahng (co-inventor of the MOSFET itself) and Simon M. Sze realized they could give a transistor permanent memory by inserting a second, electrically isolated layer inside the insulating oxide sandwich, directly between the Control Gate above and the silicon channel below.

Over the history of flash storage, engineers have built this isolated storage island in two ways:

1. Planar Floating-Gate MOSFETs (1987–2013): The isolated island is a conductive pad of doped polycrystalline silicon (polysilicon). Because polysilicon is a conductor, electrons injected into the floating gate spread evenly across the plate. However, as cells shrank below 15 nm, floating gates hit a physical wall: a single atomic pinhole defect anywhere in the bottom tunnel oxide could drain the entire conductive plate at once, and electrostatic cross-talk between adjacent floating gates corrupted neighboring bits.
2. 3D Charge-Trap Flash / V-NAND (2013–Present): Modern SSDs replace the conductive polysilicon plate with an insulating film of Silicon Nitride (Si₃N₄)—often arranged in a TANOS stack (Tantalum Nitride gate / Al₂O₃ blocking oxide / Si₃N₄ trap layer / SiO₂ tunnel oxide / Silicon channel) wrapped cylindrically around vertical channels stacked 176 to 232+ layers high. Because Si₃N₄ is a dielectric crystal rich in localized atomic electron traps, injected electrons stay pinned where they land—like marbles pressed into a waffle iron. Even if a localized defect forms in the tunnel oxide, the remaining electrons cannot flow laterally to leak out.

Electrostatic Screening: How Charge Encodes 1 and 0

Why does trapping electrons inside that middle layer store a bit? Because of electrostatic screening (Gauss's Law).

Suppose an empty (erased) flash cell has a natural threshold voltage of V_{th, erased} = +1.0 V. Whenever you apply +2.5 V to the Control Gate, the gate's positive electric field easily penetrates down to the silicon channel, turns the transistor ON, and current flows. By universal flash convention:

• Erased State (No trapped electrons, Low V_th) = Logical 1
• Programmed State (Electrons trapped in island, High V_th) = Logical 0

Now suppose we inject a packet of negative charge Q_trap < 0 (say, 300 electrons, or Q_trap ≈ −4.8 × 10⁻¹⁷ Coulombs) into the floating gate or charge-trap layer. Those negatively charged electrons sit directly between the Control Gate and the silicon channel. Their negative electric field cancels out (screens) part of the positive electric field coming from the Control Gate above.

Quantitatively, the transistor's threshold voltage shifts upward in direct proportion to the trapped charge divided by the capacitance C_CG between the Control Gate and the storage layer:

Because Q_trap is negative, Δ V_th is positive. If C_CG = 16 attofarads (1.6 × 10⁻¹⁷ F), trapping just 300 electrons raises the transistor's threshold voltage by:

The programmed cell now requires V_{th, programmed} = +1.0 V + 3.0 V = +4.0 V on its Control Gate before it will turn on!

Non-Destructive Reading

Unlike DRAM—where reading a cell discharges its capacitor and destroys the stored bit—reading a flash cell is completely non-destructive:

1. The memory controller applies an intermediate Read Reference Voltage (V_read = +2.5 V) to the cell's Control Gate.
2. If the cell is Erased (1): Its threshold voltage is +1.0 V. Since V_read (+2.5 V) > V_th (+1.0 V), the channel turns ON and current flows down the bitline. A sense amplifier detects the current and outputs a 1.
3. If the cell is Programmed (0): Its threshold voltage is +4.0 V. Since V_read (+2.5 V) < V_th (+4.0 V), the trapped electrons repel channel electrons and keep the transistor OFF. Zero current flows down the bitline, and the sense amplifier outputs a 0.

Throughout this entire read operation, the +2.5 V gate bias is far too weak to disturb the trapped electrons inside the nitride layer. You can read the cell billions of times without draining its charge.

2. Crossing a Solid Wall: Fowler–Nordheim Quantum Tunneling

How do those 300 electrons cross a solid, 8-nanometer-thick wall of silicon dioxide (SiO₂) in the first place, and why don't they leak back out?

Silicon dioxide is one of the finest electrical insulators in nature, with a wide electronic bandgap of E_g ≈ 8.9 eV. At the interface between the silicon channel and the SiO₂ tunnel oxide, an electron in the silicon conduction band faces a steep vertical potential energy cliff of height φ_B ≈ 3.15 eV.

At normal room temperature (300 K), the average thermal kinetic energy of an electron in silicon is only:

According to classical physics, an electron with 0.026 eV of kinetic energy attempting to surmount a 3.15 eV wall is like a ping-pong ball bouncing on the floor trying to jump over Mount Everest. Under normal powered or unpowered conditions, the rectangular barrier is 8 nm thick all the way across, and the probability of an electron escaping is effectively zero.

Tilting the Barrier with 10 Million Volts per Centimeter

In quantum mechanics, however, an electron is not a hard billiard ball; it is a probability wavefunction ψ(x) governed by the Schrödinger equation. When a wavefunction encounters a potential energy barrier higher than its own energy (V(x) > E), the wavefunction does not drop to zero instantaneously at the wall boundary. Instead, it penetrates into the barrier, decaying exponentially with distance x:

Across a full 8 nm rectangular barrier, that exponential decay reduces the transmission probability |ψ|² to roughly 10⁻³⁵—which is why your unpowered SSD holds its data for years.

In 1928, physicists Ralph H. Fowler and Lothar Nordheim proved that an intense external electric field changes the shape of the barrier itself:

1. Program (Write 1 → 0): When the SSD controller wants to inject electrons into the cell, on-chip Dickson charge pumps step up the motherboard's 3.3 V supply to a high programming pulse of V_prog ≈ +18 V to +20 V on the Control Gate while holding the silicon channel at 0 V.
2. Dividing 8 V to 10 V of that drop across an 8 nm (8 × 10⁻⁷ cm) tunnel oxide produces a ferocious electric field of E ≈ 10 MV/cm (10 million volts per centimeter, or 1 volt per nanometer)—thirty times the dielectric breakdown strength of dry air!
3. Because electric potential drops linearly with distance (V(x) = φ_B − qEx), this 10 MV/cm field tilts the flat rectangular top of the 3.15 eV oxide barrier into a steep right triangle.
4. Instead of facing an 8 nm-wide wall, electrons at the silicon conduction band edge now see a triangular wedge whose horizontal thickness at their energy level is only d_tunnel = φ_BqE ≈ 2.5 to 3.0 nm!

Across a 2.8 nm triangular wedge, the electron's decaying wavefunction reaches the far side with significant amplitude, emerging into the oxide conduction band and sweeping straight into the Si₃N₄ charge-trap layer.

The resulting Fowler–Nordheim tunneling current density (J_FN) obeys the Fowler–Nordheim equation:

Look closely at the exponential factor exp(−B/E), where the electric field E sits in the denominator of the exponent. That single mathematical relationship is the secret of all flash memory:

• At Read or Idle (E < 1 MV/cm): exp(−B/E) is vanishingly small; leakage timescales exceed decades.
• At Program or Erase (E ≈ 10 MV/cm): Increasing the voltage by 6× boosts the tunneling current by more than 20 orders of magnitude, moving hundreds of electrons across the solid insulator in a few hundred microseconds.
• Erase (0 → 1): To flush the electrons back out, the controller reverses the polarity—holding the Control Gate at 0 V while applying +20 V to the silicon substrate/channel. The triangular barrier tilts the opposite way, and the trapped electrons quantum-tunnel back out into the channel.

3. Storing Multiple Bits in One Transistor: SLC, MLC, TLC, and QLC

If a flash cell simply checked whether electrons were present or absent, each transistor could store only 1 bit (2¹ = 2 states: 1 or 0). That architecture is called SLC (Single-Level Cell).

As demand for terabyte-scale SSDs exploded, engineers realized that the threshold voltage V_th of a flash transistor is not inherently binary—it is a continuous analog quantity proportional to the exact number of electrons trapped in the nitride layer. If you can control the trapped charge to within a few dozen electrons, you can slice a single 4.5-volt operating window into 4, 8, or 16 non-overlapping voltage distributions, storing multiple digital bits inside a single physical transistor:

How does an SSD controller inject precisely the right number of electrons to land inside one of 16 narrow voltage bands in a QLC cell without overshooting?

It uses Incremental Step Pulse Programming (ISPP). Instead of blasting the cell with a single long +20 V pulse, the controller applies a staircase of very short voltage pulses (starting at, say, +14.0 V and stepping up by Δ V_step = +0.2 V on each step). Between every single programming pulse, the controller performs a fast Verify Read to measure the cell's current threshold voltage V_th. The instant a cell's V_th crosses into its target band, the controller raises that cell's bitline voltage to inhibit further tunneling while neighboring cells continue receiving staircase pulses.

Because TLC requires calibrating 8 states (7 verify thresholds) and QLC requires calibrating 16 states (15 verify thresholds) with tiny Δ V_step increments, QLC writes are substantially slower than SLC writes—which is why almost every modern TLC or QLC SSD reserves a portion of its flash blocks to operate in fast 1-bit Pseudo-SLC (pSLC) cache mode to absorb burst writes at 5,000 to 7,400 MB/s before folding the data into TLC/QLC blocks during idle time.

4. The NAND String and the Page-Write / Block-Erase Asymmetry

Why is SSD storage specifically called NAND flash?

In 1987, Dr. Fujio Masuoka at Toshiba invented two flash array topologies: NOR Flash and NAND Flash.

• In NOR Flash, every memory cell has its own direct metal contact to the bitline and source line in parallel (like the pull-down transistors of a CMOS NOR gate). This allows fast random access to any individual byte—making NOR flash ideal for storing small motherboard BIOS/UEFI boot firmware chips—but all those metal contacts consume huge amounts of silicon area.
• In NAND Flash, Masuoka eliminated the metal contacts between individual cells and wired 64, 128, or 256 flash transistors in series head-to-tail along a single vertical channel string—just like the series pull-down transistors of a CMOS NAND gate.

Wiring hundreds of cells in series cuts silicon area per bit dramatically, enabling terabyte SSDs. However, this series wiring—combined with shared substrate wells—creates two profound architectural rules that govern everything an SSD does.

Rule 1: Pass-Through Reads (V_pass)

Because 128 cells sit in series along a single string, current can flow from the source to the bitline sense amplifier only if every single transistor in the string conducts.

When the controller wants to read a single target cell on Wordline k, it applies the sensitive Read Reference Voltage (V_read ≈ 2.5 V) only to Wordline k. At the exact same moment, it drives all the other 127 unselected wordlines in that series string to a high Pass-Through Voltage (V_pass ≈ +6 V to +8 V)—high enough to force those 127 transistors fully ON regardless of whether they hold a 0 or a 1, turning them into transparent pass-through wires so the bitline current depends solely on the state of cell k.

Rule 2: You Can Write a Page (16 KB), But You Must Erase a Block (4–16 MB)

Across thousands of parallel NAND strings, all the cells sharing the same horizontal Wordline form a Page (typically 16 KB of user data plus ~2 KB of out-of-band error-correction parity metadata). And hundreds of pages stacked together inside a shared electrical well form an Erase Block (typically 256 to 1,024 pages, or 4 MB to 16 MB).

This physical hierarchy creates the Erase-Before-Write Asymmetry of NAND flash:

Why can't you erase a single 16 KB page without wiping its 511 neighboring pages in the same block? Because erasing requires raising the shared semiconductor channel/well of the entire block to +20 V. Selective programming (1 → 0) can be controlled per cell by boosting individual wordlines and inhibiting bitlines, but bulk erasure (0 → 1) flushes every cell in the shared block simultaneously.

Consequently, NAND flash memory is physically incapable of overwriting a byte or a page in place. To change a single 0 back to a 1 inside an already-written 16 KB page, the entire 8 MB Erase Block containing that page would have to be wiped first.

5. The Flash Translation Layer (FTL), Garbage Collection, and TRIM

If NAND flash cannot overwrite a 4 KB file block in place, how do operating systems like Linux (ext4), Windows (NTFS), and macOS (APFS) modify files millions of times a day without pausing for 5 milliseconds on every small write to erase an entire 8 MB block?

The answer is that your computer's operating system never speaks to raw NAND flash. When you open an NVMe SSD, you find not only NAND flash packages, but also a powerful multi-core ARM or RISC-V processor (the SSD Controller) paired with its own dedicated DRAM chip (1 GB of DRAM per 1 TB of NAND on high-end drives).

This onboard computer runs firmware called the Flash Translation Layer (FTL), which virtualizes the physical flash geometry into the illusion of an ordinary, in-place-overwritable block device:

Write Amplification Factor (WAF) and Why TRIM Matters

Notice what happens during Garbage Collection (GC): before the FTL can erase a partially stale block to reclaim its space, it must first read every still-valid page in that block and rewrite those valid pages to a new block.

This internal data copying means the physical NAND flash chips always write more bytes than the host operating system actually sent over the PCIe bus. Engineers quantify this overhead as the Write Amplification Factor (WAF):

If your operating system writes 10 GB of random 4 KB database updates, and Garbage Collection has to copy 20 GB of surviving valid pages out of fragmented blocks to make room, the physical NAND experiences 30 GB of writes (WAF = 3.0)—multiplying wear by 3× and cutting sustained write throughput to a third.

This explains why the SATA TRIM / NVMe Deallocate command is essential:

• When you delete a 20 GB video file in your operating system, the filesystem does not overwrite those 20 GB with zeros; it simply deletes the pointer in its own filesystem metadata table.
• Without TRIM, the SSD's FTL has no idea that those 20 GB of physical pages now belong to a deleted file. During Garbage Collection, the SSD will dutifully treat those 20 GB of dead video chunks as "Valid" data, reading and rewriting them from block to block forever!
• With TRIM / Deallocate, the operating system immediately notifies the SSD controller: "LBA range X through Y is no longer in use." The FTL flips those physical pages to Stale (Invalid) in its DRAM bitmap immediately. When Garbage Collection visits those blocks, it skips copying the deleted pages entirely, keeping WAF low and preserving high write speeds.

To further reduce WAF, all SSDs reserve 7% to 28% Over-Provisioning (OP)—hidden physical flash capacity beyond the user-visible drive size (for example, a chip containing 1,024 GiB of raw NAND is sold as a 1,000 GB / 931 GiB drive)—so the Garbage Collector always has breathing room of free blocks even when the user thinks the drive is "99% full."

6. How SSDs Fail: Oxide Wearout, Wear Leveling, and Unpowered Data Retention

Because Fowler–Nordheim tunneling forces energetic electrons directly through a solid 8 nm silicon dioxide crystal under a 10 MV/cm electric field, flash memory experiences cumulative physical wear every time a block is programmed and erased.

1. Tunnel Oxide Trap Accumulation (P/E Cycle Wearout)

Every Program/Erase (P/E) cycle breaks a tiny fraction of covalent Si–O bonds inside the tunnel oxide, creating permanent atomic defects (interface states and bulk oxide traps). These defects degrade the cell in two ways:

1. Threshold Window Closure: Electrons get permanently stuck inside the broken oxide bonds of the tunnel barrier itself, shifting the erased baseline voltage upward and narrowing the usable gap between states.
2. Stress-Induced Leakage Current (SILC): Chains of atomic defects form microscopic stepping-stone pathways through the 8 nm oxide, allowing trapped electrons to leak back out via trap-assisted tunneling even at 0 V.

Eventually, after roughly 500–1,000 P/E cycles for QLC, 1,500–3,000 cycles for 3D TLC, or 50,000–100,000 cycles for SLC, the raw bit error rate exceeds what even the controller's Low-Density Parity-Check (LDPC) error-correcting hardware can repair, and the block is retired into a spare pool.

To prevent frequently updated files (like OS log files) from burning through a single physical block in days while the rest of the drive sits untouched, the FTL enforces Dynamic and Static Wear Leveling—tracking the exact P/E cycle count of every physical block and periodically migrating cold, static files (like old photos or OS binaries) onto high-wear blocks so their low-wear blocks can enter active rotation.

2. The Temperature Paradox & Unpowered Cold-Storage Decay

Wait—if SSDs are non-volatile, can you copy your family archives onto an SSD, put it in a safe deposit box for 25 years, and expect every file to read back cleanly?

No—especially if the drive is worn and the storage environment is warm.

Electrons trapped inside a charge-trap layer obey Arrhenius thermal activation: the higher the ambient temperature T, the more thermal vibrational energy (k_B T) the silicon lattice transfers to trapped electrons, exponentially accelerating their escape through oxide defects:

This creates a famous Temperature Paradox in solid-state physics:

• High Temperature During Programming (55^∘C–70^∘C) is Beneficial: Thermal energy during the +20 V write pulse actually anneals (heals) strained Si–O bonds in the tunnel oxide, reducing P/E cycle wear!
• High Temperature During Unpowered Storage is Destructive: Every 10^∘C rise in ambient storage temperature roughly cuts unpowered data retention time in half.

Under the JEDEC JESD218 solid-state drive standard, a brand-new SSD with minimal oxide wear can retain data unpowered at room temperature (20^∘C) for 5 to 10+ years. However, once an SSD has reached its rated end-of-life endurance (when its tunnel oxides are full of trap-assisted leakage paths), JEDEC only requires:

• Client (Consumer) SSDs at End-of-Life: 1 year of unpowered retention at 30^∘C (86^∘F).
• Enterprise SSDs at End-of-Life: 3 months of unpowered retention at 40^∘C (104^∘F).

When an SSD remains powered on in a computer or server, its controller periodically scans blocks in the background (** Patrol Read / Read Scrubbing**): if LDPC error correction detects that a block's voltage distributions are drifting due to charge leakage or Read Disturb (weak tunneling induced on neighboring pages by repeated +7 V V_pass reads), the FTL refreshes the data into a fresh block before any uncorrectable bit errors occur.

Related Explainers

• How Semiconductors and Transistors Work — How doping silicon with boron and phosphorus creates p-n junctions and MOSFET voltage switches.
• How Computer Memory (RAM) Actually Works — Why volatile 1T1C DRAM cells trade persistence for 14-nanosecond speed and require continuous refresh cycles.
• How CPU Cache Hierarchies Overcome the Memory Wall — How 6-transistor SRAM caches bridge the latency gap between CPU registers and main memory.
• How Operating Systems Run Software — How virtual memory, page tables, and filesystems translate application reads and writes into block storage requests.