How a CPU Executes an Instruction

When you write a line of computer code such as:

total = price + tax

it feels abstract, mathematical, and weightless. You press a button, and within a microsecond, the calculation is done.

Yet inside the silicon microprocessor beneath your keyboard, nothing is abstract.

To execute that single line of code, thousands of physical electrical signals surged across microscopic copper bus wires. Millions of electrons flowed through semiconductor logic gates. Storage registers latched electrical charges, an Arithmetic Logic Unit resolved binary potentials, and the result was stamped into memory.

A computer processor is not a brain. It is an ultra-fast, mechanical assembly line synchronized by an electronic clock.

In How Binary and Logic Gates Became Computation, we discovered how physical transistors combine to create logic gates (AND, OR, NOT, XOR) and arithmetic adders.

Now, we step up to the next architectural summit: How do those logic gates assemble into a complete, self-directed Central Processing Unit (CPU) capable of executing computer software?

                     THE FIVE STAGES OF THE CPU INSTRUCTION PIPELINE
  
  1. Instruction Fetch (IF)  2. Instruction Decode (ID) 3. Execute / ALU (EX)    4. Memory Access (MEM)   5. Register Writeback (WB)
    Program Counter (PC)      Opcode decoded into        ALU computes arithmetic   Loads from or stores     Result stamped into
    fetches bytes from RAM    physical control signals   result across adders      data to L1/RAM cache     destination register

The diagram below traces the five-stage pipeline through which a modern CPU executes an instruction:

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1. The Machine Code Illusion: What an Instruction Actually Is

Software does not run on hardware directly.

Before your computer can execute total = price + tax, a compiler program (such as GCC, Clang, or Python's bytecode engine) translates that human statement into machine language—a sequence of raw binary numbers.

Consider a simple assembly language instruction for an ARM or RISC-V processor:

ADD R1, R2, R3

This instruction tells the CPU: "Take the number stored in Register 2, add it to the number stored in Register 3, and save the result into Register 1."

When this instruction is compiled into binary machine code, it becomes a 32-bit number:

               THE ANATOMY OF A 32-BIT MACHINE INSTRUCTION (RISC-V)
  
       Opcode (7 bits)   rd (5 bits)   funct3 (3)   rs1 (5 bits)   rs2 (5 bits)   funct7 (7)
      ┌───────────────┬─────────────┬────────────┬──────────────┬──────────────┬──────────────┐
      │    0110011    │    00001    │    000     │    00010     │    00011     │   0000000    │
      └───────────────┴─────────────┴────────────┴──────────────┴──────────────┴──────────────┘
             ▲               ▲                          ▲              ▲
             │               │                          │              │
        "I am an ADD"   Destination:               Source Reg 1:  Source Reg 2:
                        Register R1                Register R2    Register R3

Notice what a machine instruction really is: it is a physical wiring configuration template.

When those thirty-two bits enter the CPU, they are not read as text. They are applied directly to thirty-two physical copper wires as electrical voltages (0 volts for 0, and 1.2 volts for 1).

Those voltages physically configure the internal routing of the chip for the next clock cycle.

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2. The Physical Anatomy of a CPU

Inside every microprocessor, regardless of whether it is an Intel x86 chip in a server or an Apple ARM chip in an iPhone, you will find five core organs:

               THE INTERNAL BLOCK DIAGRAM OF A SIMPLE CPU
  
                        ┌──────────────────────────────┐
                        │      PROGRAM COUNTER (PC)    │ ── (Holds Memory Address)
                        └──────────────┬───────────────┘
                                       │
                                       ▼ Address Bus
                        ┌──────────────────────────────┐
                        │   INSTRUCTION MEMORY / L1    │ ── (RAM Cache)
                        └──────────────┬───────────────┘
                                       │
                                       ▼ Data Bus
                        ┌──────────────────────────────┐
                        │     INSTRUCTION REGISTER     │
                        └──────────────┬───────────────┘
                                       │
                                       ▼
                        ┌──────────────────────────────┐
                        │      INSTRUCTION DECODER     │ ──▶ Control Signals (Wire Activations)
                        └──────────────┬───────────────┘
                                       │
               ┌───────────────────────┴───────────────────────┐
               ▼                                               ▼
     ┌───────────────────┐                           ┌───────────────────┐
     │   REGISTER FILE   │ ── Operands A & B ──────▶ │  ARITHMETIC LOGIC │
     │  (R0, R1, R2...)  │                           │    UNIT (ALU)     │
     └─────────▲─────────┘                           └─────────┬─────────┘
               │                                               │
               └─────────────── Result Writeback Bus ──────────┘

1. The Register File: A collection of ultra-fast internal memory cells (typically 16, 32, or 64 registers) located directly on the processor die. Each register is built from high-speed transistor flip-flops and can deliver a number in less than 200 picoseconds.
2. The Program Counter (PC): A specialized register that stores the memory address of the instruction currently being executed.
3. The Instruction Register (IR): A temporary holding latch that stores the binary instruction bytes fetched from memory.
4. The Instruction Decoder (Control Unit): A combinational logic circuit that examines the opcode bits and switches on the appropriate electrical pathways inside the processor.
5. The Arithmetic Logic Unit (ALU): The calculating muscle containing adders, subtractors, and bit-shifters (explored in How Binary and Logic Gates Became Computation).
6. The Bus: Parallel lines of microscopic metal traces that transport addresses, instructions, and data between registers and the ALU.

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3. The Heartbeat: Why CPUs Need a Clock

Before examining how an instruction runs, we must understand the processor's heartbeat: the clock.

As explored in How Clocks Actually Measure Time, quartz oscillators generate stable, periodic frequencies. Modern processors contain clock distribution trees that pulse a square wave between 0 volts and high voltage billions of times per second (e.g. 3.5 GHz = 3.5 billion ticks/second):

               THE SQUARE-WAVE CPU CLOCK SIGNAL (3.5 GHz)
  
      Voltage
        ▲
        │    Rising Edge                     Rising Edge
   1.2V ┼       ┌─────┐                         ┌─────┐
        │       │     │                         │     │
     0V ┼───────┘     └─────────────────────────┘     └─────────▶ Time
        │       ◀───── 1 Clock Period: ~0.28 nanoseconds ──────▶

Why Can't a CPU Run Without a Clock?

Why not let the electrons flow continuously at maximum speed?

Because of propagation delay and race conditions.

When electrical signals travel through thousands of logic gates in an ALU, they do not arrive instantly. An electrical pulse takes roughly a few picoseconds to traverse a transistor. Because some paths have more gates than others, signals arrive at different times:

• If a signal takes Path A through three gates, it arrives in 10 picoseconds.
• If a signal takes Path B through twelve gates, it arrives in 40 picoseconds.

During those intermediate thirty picoseconds, the output wires of the adder are fluctuating wildly through garbage values.

The clock acts as a strict military traffic commander:

1. It says: "Nobody look at the outputs yet! The signals are still settling."
2. It waits for the electrical signals to stabilize across all gates.
3. On the rising edge of the clock wave, it snaps open storage latches (flip-flops) for a fraction of a picosecond, captures the settled voltages, and locks them in place.

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4. The Five Stages of the Instruction Cycle

Now let us follow the journey of a single instruction through the classic Five-Stage RISC Pipeline:

   ADD R1, R2, R3   (Machine Code: 0x003100B3)

Stage 1: Instruction Fetch (IF)

At the start of the clock tick:

1. The Program Counter (PC) holds a memory address (for example, 0x00400000).
2. This address is placed onto the memory Address Bus.
3. The processor's Level 1 (L1) Instruction Cache looks up address 0x00400000, retrieves the 32-bit binary number stored there (0x003100B3), and places it onto the Data Bus.
4. The bits are latched into the processor’s Instruction Register (IR).
5. In parallel, a simple hardware adder increments the Program Counter by 4 bytes (PC ← PC + 4), pointing it toward the next instruction in memory.

Stage 2: Instruction Decode (ID)

The 32 bits sitting in the Instruction Register are wired directly into the Instruction Decoder:

1. The decoder looks at the lowest 7 bits (the opcode 0110011). The logic gates inside the decoder identify this pattern: "This is an ALU register-to-register operation."
2. The decoder examines the next 3 bits (funct3 = 000) and the top 7 bits (funct7 = 0000000): "This is an ADD operation."
3. The decoder extracts the register address bits:
   • Source 1: 00010 (Register R2)
   • Source 2: 00011 (Register R3)
   • Destination: 00001 (Register R1)
4. The decoder activates the control lines of the Register File. The voltages stored in Register R2 (say, the number 42) and Register R3 (the number 58) are placed onto the internal ALU input buses.

Stage 3: Execute (EX)

The operands from R2 and R3 enter the Arithmetic Logic Unit:

1. The Instruction Decoder sends an electrical control code to the ALU: ALU_OP = ADD.
2. Inside the ALU, multiplexers route the voltages from R2 and R3 into thirty-two cascaded full-adders.
3. The binary addition ripples across the adder circuits:

4. The binary representation of 100 (0000...01100100) stabilizes on the ALU output bus.

Stage 4: Memory Access (MEM)

This stage is used only for LOAD and STORE instructions that need to read from or write to main RAM:

• If this were a LOAD instruction (e.g. LOAD R1, [R2 + 8]), the ALU's output would be used as a memory address to fetch data from RAM.
• But because our instruction is a pure register-to-register ADD, the memory stage does nothing. The control unit keeps the memory write-enable line turned OFF, and the ALU result passes straight through to the next stage.

Stage 5: Register Writeback (WB)

On the final clock tick of the instruction:

1. The control unit asserts the Write-Enable signal on Register R1.
2. The ALU output bus (carrying the binary number 100) is connected to the input pins of Register R1.
3. The internal flip-flops of Register R1 latch the voltage.
4. The value of R1 is now permanently updated to 100.

The instruction is complete. The processor is already executing the next instruction.

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5. Pipelining: The Automobile Assembly Line

In early processors from the 1970s (such as the MOS 6502 or Intel 8080), a CPU finished all five stages of one instruction before starting the next. If each stage took one clock cycle, an instruction took five cycles to complete.

In the 1980s, computer architects like John Hennessy (Stanford) and David Patterson (UC Berkeley) pioneered instruction pipelining.

Think of a commercial laundromat:

               THE LAUNDRY PIPELINE ANALOGY
  
   Sequential Laundry (No Pipelining):
   Wash Load 1 (30m) ──▶ Dry Load 1 (30m) ──▶ Fold Load 1 (30m)  [Total: 90 mins for 1 load]
   Wash Load 2 (30m) ──▶ Dry Load 2 (30m) ──▶ Fold Load 2 (30m)  [Total: 180 mins for 2 loads]
  
   Pipelined Laundry (Overlap):
   Load 1:   [ Wash ] ──▶ [ Dry  ] ──▶ [ Fold ]
   Load 2:                [ Wash ] ──▶ [ Dry  ] ──▶ [ Fold ]
   Load 3:                             [ Wash ] ──▶ [ Dry  ] ──▶ [ Fold ]
  
   After the pipeline fills, ONE LOAD COMPLETES EVERY 30 MINUTES!

A pipelined CPU applies this exact principle to instructions:

               THE 5-STAGE CPU PIPELINE EXECUTION GRID
  
   Clock Cycle:     1       2       3       4       5       6       7
  ───────────────────────────────────────────────────────────────────────
   Instruction 1:  [ IF ]  [ ID ]  [ EX ]  [ MEM]  [ WB ]
   Instruction 2:          [ IF ]  [ ID ]  [ EX ]  [ MEM]  [ WB ]
   Instruction 3:                  [ IF ]  [ ID ]  [ EX ]  [ MEM]  [ WB ]
   Instruction 4:                          [ IF ]  [ ID ]  [ EX ]  [ MEM]
   Instruction 5:                                  [ IF ]  [ ID ]  [ EX ]

• In Cycle 1, Instruction 1 is Fetched.
• In Cycle 2, Instruction 1 is Decoded, while Instruction 2 is Fetched.
• In Cycle 3, Instruction 1 is Executed, Instruction 2 is Decoded, and Instruction 3 is Fetched.
• By Cycle 5, all five stages of the CPU are working simultaneously on five different instructions!

Even though any single instruction takes five clock cycles from start to finish (latency), the CPU completes one full instruction every single clock cycle (throughput: CPI ≈ 1).

At a clock speed of 3.5 GHz, the CPU completes 3.5 billion instructions every second.

A Worked Numerical Example: Clock Frequency, IPC, and Memory Stall Latency

To understand why a modern processor cannot achieve its theoretical maximum speed on arbitrary software, let us calculate the real execution time of a program loop across real silicon microarchitecture parameters:

Suppose a modern high-performance CPU core runs at a clock frequency of f = 4.0 GHz (4.0 × 10⁹ cycles per second). The duration of a single clock cycle (clock period τ) is:

In 250 picoseconds, light in a vacuum travels just 7.5 centimeters—and inside silicon metal interconnects, electrical signals travel barely 3.5 cm.

Now suppose a loop executes a workload of N = 10⁹ instructions (1 billion instructions).

1. The Ideal Superscalar Pipeline Case

In an ideal 4-wide out-of-order superscalar core running compute-only integer arithmetic with zero cache misses and zero branch mispredictions, the processor can retire an average of IPC_ideal = 2.0 instructions per cycle, yielding an ideal Cycles Per Instruction of:

Under these ideal conditions, the billion instructions require:

2. The Real Memory Penalty: Caches vs. DRAM

In real code, arithmetic instructions depend on data residing in memory. Suppose 25% (0.25) of all instructions are memory LOAD or STORE operations.

Accessing data across the memory hierarchy incurs radically different cycle penalties:

• L1 Data Cache Hit (32 KB, on-core): 4 clock cycles (1.0 ns).
• L2 Cache Hit (1 MB, per-core): 14 clock cycles (3.5 ns).
• L3 Shared Cache Hit (32 MB): 48 clock cycles (12.0 ns).
• Main Memory (DDR5 DRAM): 240 clock cycles (60.0 ns).

Suppose the program achieves a typical cache profile:

• 90% of memory accesses hit in the fast L1 cache (zero additional stall cycles beyond baseline execution).
• 7% miss L1 but hit L2 (14 cycles penalty).
• 2% miss L2 but hit L3 (48 cycles penalty).
• 1% miss all on-chip caches and must fetch from external DRAM (240 cycles penalty!).

The average memory stall cycles per instruction (Stall_mem) is:

Notice the dramatic impact of that single 1% DRAM miss rate: it alone contributes 0.25 × 2.40 = 0.60 stall cycles—more than all L1, L2, and L3 cache accesses combined!

3. Total Effective Execution Time

Adding memory stall cycles to the base processor cycles yields the effective CPI:

The total execution time for the billion instructions becomes:

Because of memory latency alone, execution time increased from 125 ms to 396 ms—a 3.17× slowdown!

This mathematical reality explains why modern computer architecture focuses obsessively on multi-level caching, out-of-order execution, and hardware branch predictors: in modern computing, the fastest arithmetic unit in the world is useless if it spends two-thirds of its time sitting idle waiting for bytes to crawl across the memory bus from DRAM.

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6. Pipeline Hazards: When the Assembly Line Stalls

Pipelining is brilliant, but it creates profound engineering vulnerabilities called pipeline hazards:

                               THE THREE PIPELINE HAZARDS
  
  Hazard Type      Physical Cause                                  Modern Hardware Resolution
  ──────────────────────────────────────────────────────────────────────────────────────────
  Data Hazard      Instruction 2 needs the result of Inst 1        Forwarding (Bypassing ALU result
                   before Inst 1 has finished Writeback!           directly to input; or pipeline stall)
  
  Structural Haz.  Two instructions need the exact same physical   Separate L1 Instruction Cache
                   hardware resource at the exact same cycle       and L1 Data Cache (Harvard split)
  
  Control Hazard   A conditional branch (IF/ELSE) changes PC;     Branch Prediction & Speculative
                   CPU doesn't know which code to fetch next!      Execution (Guessing branch target)

The Control Hazard and Branch Prediction

The most dangerous hazard is the conditional branch (if/else statements in code):

CMP R1, 0          ; Is R1 equal to zero?
BEQ target_address ; If yes, branch to target_address!
ADD R2, R3, R4     ; Else, continue here...

When the CPU fetches BEQ (Branch if Equal), it cannot know whether the branch will be taken until Stage 3 (Execute) compares the numbers.

What should the CPU fetch during Cycles 2 and 3?

• If it stops and waits, the pipeline empties (a pipeline stall or bubble), destroying performance.
• Modern processors deploy Branch Predictors—sophisticated neural and pattern-matching circuits that track execution history and guess with over 95% accuracy which path the program will take.
• The CPU speculatively executes instructions down the predicted path before it knows for sure if the branch was taken!
• If the guess was correct: zero performance lost.
• If the guess was wrong (a branch misprediction): the CPU must instantly flush all pipeline stages, discard the speculative results, and restart from the correct address, paying a penalty of 15 to 20 clock cycles.

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7. Beyond the Single Core: Superscalar and GPUs

Modern high-performance processors push this architecture to staggering extremes:

1. Superscalar Execution: Modern CPUs (like Apple M-series or AMD Zen) are not single pipelines. They are wide out-of-order superscalar engines with six to eight parallel execution pipelines. The CPU fetches eight instructions per cycle, analyzes their dependencies in real-time, reorders them, executes them across multiple ALUs simultaneously, and reassembles them in correct order.
2. Graphics Processing Units (GPUs): While a CPU is optimized to execute a single, complex thread of branching instructions with ultra-low latency, a GPU takes the opposite approach. A GPU packs thousands of small, simple ALUs onto a single chip. It cannot run an operating system efficiently, but it can execute thousands of identical additions and multiplications simultaneously (SIMD: Single Instruction, Multiple Data).

As explored in How Large Language Models Generate Text, modern artificial intelligence models (such as LLMs and neural networks) are nothing more than billions of matrix multiplications. They run on GPUs because thousands of ALUs execute the exact same fetch-decode-execute cycle across billions of weights in parallel.

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8. Summary: From Sand to Thought

Layer	Physical Reality	Intellectual Breakthrough
Material	Purified Silicon (SiO2)	Chemical crystallization and photolithographic etching
Physics	Controlled Electron Drift	Quantum semiconductor bandgaps and field-effect gates
Logic	Logic Gates (NAND, XOR, AND)	George Boole's algebra & Claude Shannon's switching circuits
Arithmetic	Half-Adders & Full-Adders	Binary addition via XOR sum and AND carry extraction
Microarchitecture	Registers, Buses, Decoders, ALU	Clocked edge-triggered latches & instruction pipelines
Software	Machine Code Bytes	Stored-program architecture; compiler code generation

From a handful of river sand to a microchip executing billions of instructions per second, computing is the physical embodiment of mathematical logic.

Every high-level software application—translated from human source code into machine opcodes by How Compilers Translate Human Code into Machine Instructions—is executed on billions of nanoscale MOSFET gates patterned onto silicon via How Photolithography Prints Billions of Transistors on a Silicon Wafer using the solid-state physics of How Semiconductors and Transistors Work.

Every pixel on your screen, every byte retrieved from volatile silicon capacitors in How Computer Memory (RAM) Actually Works or non-volatile charge traps in How Solid-State Drives (SSDs) and Flash Memory Store Data Without Power, every hardware privilege ring enforced by How an Operating System Actually Runs Software, every query evaluated in How Search Engines Actually Work, and every autonomous decision made in How AI Agents Work rests upon this five-stage mechanical journey executed billions of times every second.