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ComputingTopic Knowledge Hub

Computing & Digital Architecture

From mechanical calculation to modern digital computers: binary logic, CPU instruction cycles, memory hierarchies, and operating systems.

22 Published Explainers
82 Systems Analyzed
192 Core Concepts
3 Inquiry Path
Recommended Starting Point

How OTP and Two-Factor Authentication Actually Work

From shared cryptographic secrets and Unix timestamps to dynamic truncation and SMS delivery risks

Core Question Answered
“How can an authenticator app generate the exact 6-digit code as a server without any internet connection?”
Time-Based One-Time Password (TOTP)HMAC-SHA1Shared Secret KeyUnix Epoch Time
Read Explainer

Inquiry Learning Paths

Structured sequences designed to take you from a familiar question to complete first-principles understanding.

All Learning Paths
Computing & Silicon Architecture · 8 Core Steps

How Computers Execute and Store Information

Progress from quantum band gaps in doped silicon to CMOS logic gates, binary adders, pipelined CPU instruction execution, coherent SRAM caches, and operating system kernels.

Full Path Map
Starting Question

“How does purified quartz sand doped with boron and phosphorus become a microprocessor capable of executing billions of arithmetic instructions and running an operating system every second?”

Prerequisites:Positional Place-Value Notation & Base-2 Binary NumbersElectrical Voltage Thresholds & Capacitive Charge StoragePiezoelectric Quartz Harmonic Oscillation
1

How Semiconductors and Transistors Actually Work

Explains how doping silicon crystals creates p-n junctions and voltage-controlled MOSFET switches with zero moving parts.

2

How Binary and Logic Gates Became Computation

Shows how Claude Shannon mapped George Boole’s symbolic logic onto physical on/off switches (AND, OR, NOT, XOR) to represent numbers and decisions.

3

How CMOS Transistors Form Logic Gates

Details how complementary PMOS pull-up and NMOS pull-down transistor networks implement logic gates with near-zero static power dissipation.

4

How Binary Arithmetic Logic Units Actually Add Numbers

Combines XOR and AND gates into half-adders, full-adders, and carry-lookahead circuits that perform binary addition, subtraction, and comparisons in picoseconds.

5

How a CPU Executes an Instruction

Steps through the Fetch–Decode–Execute–Writeback pipeline, register files, branch prediction, and out-of-order execution inside a modern processor core.

6

How CPU Cache Hierarchies Overcome the Memory Wall

Explains why main DRAM is hundreds of times slower than the ALU—and how L1/L2/L3 SRAM caches and MESI coherence protocols prevent processor stalls.

7

How an Operating System Actually Runs Software

Reaches the software abstraction layer: how the OS kernel uses hardware timer interrupts, virtual-memory page tables, and system calls to multiplex applications safely.

8

How Compilers Translate Human Code into Machine Instructions

Completes the journey from human thought to silicon execution: how compilers lex, parse, optimize via SSA form, and allocate hardware registers to emit native machine code.

Endpoint:You understand the entire computing stack without black boxes: how electric fields in doped silicon form CMOS logic gates, how gates compose into a clocked ALU and pipelined CPU with coherent SRAM caches, and how an operating system kernel schedules virtual-memory processes on top of that hardware.
Money, Banking & Financial Rails · 6 Core Steps

How Digital Payments and Banking Infrastructure Work

Follow money from ancient Mesopotamian credit ledgers and standardized coinage to central bank RTGS reserve accounts, EMV chip cryptograms, and instant UPI switches.

Full Path Map
Starting Question

“When you tap a credit card or scan a UPI QR code and see "Payment Successful" in under two seconds, what messages actually travel across banking switches—and when does real money move between banks?”

Prerequisites:Double-Entry Ledgers (Assets, Liabilities & Commercial Bank Deposits)Cryptographic Hash Functions (HMAC) & Asymmetric Digital SignaturesAtomic Two-Phase Commit & Deferred Netting
1

Why Humans Invented Money

Establishes the foundational insight of monetary history: credit tallies and unit-of-account ledgers preceded physical coinage by millennia.

2

How Standardized Coinage Transformed Trade

Traces how sovereign weight-and-purity stamps solved asymmetric assay verification costs and created standardized state clearing.

3

How Money Moves Between Banks

Reveals modern wholesale settlement: commercial banks do not send cash over the internet, but debit and credit reserve accounts on the central bank’s core ledger (e-Kuber RTGS and NEFT).

4

Why Bank Transfers Used to Take Hours (and Days)

Explains the engineering evolution from paper cheque truncation and half-hourly deferred net settlement batches to continuous 24x7 real-time rails.

5

How Credit Cards Actually Work

Deconstructs the dual-message four-party card model: EMV chip cryptograms (ARQC), ISO 8583 authorization holds in two seconds, and T+1 interchange batch clearing.

6

How UPI Works

Contrasts pull-based card rails with sovereign real-time push architecture: Virtual Payment Addresses, Common Library PIN encryption, atomic bank core updates, and RTGS net settlement.

Endpoint:You can distinguish instant retail authorization from central-bank reserve settlement, trace every cryptographic signature in both an EMV card tap and a UPI QR scan, and explain how commercial banks net trillions in obligations across central bank books without double-spending.
Networks & Telecommunications · 7 Core Steps

How the Internet Carries Information Around the World

Follow a network request across every physical and protocol layer: BGP autonomous systems, IP packet hops, submarine optical amplifiers, 802.11 Wi-Fi radio modulation, Anycast DNS, and TLS cryptography.

Full Path Map
Starting Question

“When you tap a link or type a web address on your phone, how do your request packets travel through air as radio waves and across ocean floors as laser pulses to fetch a webpage in milliseconds?”

Prerequisites:Binary Bitstreams & Packet Header EncapsulationElectromagnetic Spectrum (Microwave Radio vs. 1550 nm Infrared Light)Modular Arithmetic & One-Way Trapdoor Functions
1

How the Internet Actually Works

Introduces the global network of networks: 115,000+ independent Autonomous Systems exchanging reachability paths via BGP-4 and forwarding 1,500-byte packets without central control.

2

How Packets Actually Travel Across the Internet

Follows an individual packet hop-by-hop: TCP segmentation, IPv4/IPv6 TTL decrementing, longest-prefix-match TCAM lookups, and dynamic rerouting around severed links.

3

How Fiber-Optic Cables Carry Light Across Oceans

Descends to the ocean floor where 99% of intercontinental traffic travels as 1550 nm infrared laser light through silica fibers amplified every 70 km by erbium-doped optical repeaters (EDFAs).

4

How Wi-Fi Actually Works

Explains the wireless last hop: how your router maps digital bits onto 2.4/5/6 GHz QAM radio subcarriers (OFDMA) and coordinates airtime via CSMA/CA collision avoidance.

5

How Cellular Networks Route Calls and Data

Extends wireless routing to mobile wide-area telecommunications: microsecond base station MAC scheduling, RRC connection handshakes, seamless inter-tower handovers, and GTP tunnels across LTE and 5G cores.

6

What Happens When You Type a Website Address

Connects packet transport to the application layer: hierarchical Anycast DNS resolution, the TCP three-way handshake, TLS 1.3 key exchange, and browser DOM rendering.

7

How Public-Key Cryptography Actually Works

Explains the mathematical miracle behind HTTPS and TLS: how two computers that have never met establish an encrypted channel over public fiber using Diffie-Hellman and elliptic-curve cryptography.

Endpoint:You can trace a web request across every physical and protocol layer—from a capacitive finger tap and 802.11 QAM radio waves, through Anycast DNS, BGP autonomous systems, and erbium-doped submarine fiber-optic repeaters, to a TLS 1.3 elliptic-curve handshake.

All Published Explainers

Every verified first-principles analysis in this domain.

Explainer

How OTP and Two-Factor Authentication Actually Work

From shared cryptographic secrets and Unix timestamps to dynamic truncation and SMS delivery risks

First-Principles ExplainerRead
Explainer

How Binary and Logic Gates Became Computation

How George Boole mapped human thought to two numbers, Claude Shannon proved switches could do algebra, and silicon transistors turned electric currents into logic

First-Principles ExplainerRead
Explainer

Why SMS OTPs Sometimes Arrive Late or Fail Entirely

The multi-hop journey from enterprise application servers through telecommunication aggregators, SMPP queues, and cellular signaling networks

First-Principles ExplainerRead
Explainer

How a CPU Executes an Instruction

How a CPU executes machine code through the Fetch, Decode, Execute, Memory, and Writeback pipeline using registers, decoders, clock signals, and the ALU

First-Principles ExplainerRead
Explainer

How Public-Key Cryptography Actually Works

One-way mathematical trapdoors, modular clock arithmetic, Diffie-Hellman key exchange, and the RSA prime factor breakthrough

First-Principles ExplainerRead
Explainer

How PageRank and Link Analysis Rank the Web

From academic citation networks to the random surfer model, Markov transition matrices, the damping factor, and power iteration numerical convergence

First-Principles ExplainerRead
Explainer

How Computer Memory (RAM) Actually Works

Capacitor charge leakage, 1T1C bit cells, differential sense amplifiers, and the nanosecond choreography of DRAM refresh

First-Principles ExplainerRead
Explainer

How Passkeys and WebAuthn Work

From FIDO2 public-key credentials and Secure Enclave isolation to origin binding, challenge-response signatures, and synced passkeys

First-Principles ExplainerRead
Explainer

How an Operating System Actually Runs Software

Hardware privilege rings, preemptive timer interrupts, MMU virtual memory page tables, and context switching

First-Principles ExplainerRead
Explainer

How Single Sign-On (SSO), OAuth 2.0, and OpenID Connect Work

From the browser redirect dance and Proof Key for Code Exchange (PKCE) to JWT signature verification, SAML assertions, and identity provider federation

First-Principles ExplainerRead
Explainer

How Multi-Stage Search Ranking Pipelines and Learning to Rank Work

From candidate generation and BM25/vector retrieval to LambdaMART gradient boosting, cross-encoder neural re-ranking, and SERP blending

First-Principles ExplainerRead
Explainer

How CMOS Transistors Form Logic Gates

Complementary NMOS and PMOS pairs, silicon pull-up and pull-down networks, voltage transfer margins, and the physical mechanics of Boolean switches

First-Principles ExplainerRead
Explainer

How Binary Arithmetic Logic Units Actually Add Numbers

From half adders and ripple-carry latency to carry-lookahead prefix trees, two's complement subtraction, and status flag generation in physical silicon

First-Principles ExplainerRead
Explainer

How the CPU Clock Synchronizes Billions of Transistors

Quartz piezoelectric vibration, phase-locked loop multiplication, H-tree distribution grids, clock skew, and setup-and-hold timing margins

First-Principles ExplainerRead
Explainer

How CPU Cache Hierarchies Overcome the Memory Wall

6T SRAM bistable latches, spatial and temporal locality, set-associative tag matching, and MESI multicore cache coherency

First-Principles ExplainerRead
Explainer

How Solid-State Drives (SSDs) and Flash Memory Store Data Without Power

Floating-gate and charge-trap MOSFETs, Fowler–Nordheim quantum tunneling, TLC/QLC voltage windows, and the Flash Translation Layer

First-Principles ExplainerRead
Explainer

How Compilers Translate Human Code into Machine Instructions

From text tokens and abstract syntax trees to SSA intermediate representation, register allocation, and native machine code

First-Principles ExplainerRead
Explainer

How Microprocessors Execute Pipelined Instructions

From the classic 5-stage RISC pipeline and data hazards to register forwarding, branch prediction, and superscalar out-of-order execution

First-Principles ExplainerRead
Explainer

How Relational Databases Guarantee ACID Transactions Without Corrupting Data

From Write-Ahead Logging and page buffer pools to Strict Two-Phase Locking, MVCC snapshot isolation, and ARIES crash recovery

First-Principles ExplainerRead
Explainer

How Virtual Memory and the MMU Isolate Processes and Expand RAM

From bare-metal memory corruption and base-and-bound registers to multi-level page tables, TLB hardware caching, kernel page faults, and Copy-on-Write process isolation

First-Principles ExplainerRead
Explainer

How Quantum Computers Execute Algorithms

From Bloch sphere state vectors and unitary quantum logic gates to destructive interference and Shor's period-finding algorithm

First-Principles ExplainerRead
Explainer

How Hardware Security Modules (HSM) Protect Cryptographic Keys

From active zeroization envelopes and PKCS#11 isolation to PCI PTS financial PIN block translation

First-Principles ExplainerRead

Technical Systems & Protocols Analyzed

Hardware, protocol switches, and central clearing houses examined in this hub.

Authenticator AppAuthentication ServerSMS GatewayLeibniz Binary Notation SystemShannon Relay-Switching NetworkCMOS Logic Gate ArchitectureArithmetic Logic Unit (ALU) Adder CircuitGlobal Telecom Signaling Network (SS7/Diameter)Carrier SMSCDistributed Ledger Technology (DLT) GatewayVon Neumann Computer ArchitectureClassic 5-Stage RISC Instruction PipelineMicroprocessor Register File & Internal Bus SystemL1/L2 High-Speed CPU Cache HierarchyTransport Layer Security (TLS 1.3 / HTTPS)Public Key Infrastructure (PKI) & Certificate AuthoritiesSSH Secure Shell Key AuthenticationFIDO2 / WebAuthn Passkey Cryptographic Token InfrastructureWeb Graph Link Matrix EngineDistributed Sparse Matrix Power Iteration PipelineInverted Index Document Scoring PipelineSearch Ranking EngineDDR4 / DDR5 Synchronous Dynamic RAM ArchitectureMemory Controller Hub (Integrated Memory Controller - IMC)Physical Memory Bus & Double Data Rate (DDR) SignalingWebAuthn Browser JavaScript API (navigator.credentials)Operating System Platform AuthenticatorSecure Processing Unit (Secure Enclave / StrongBox)Relying Party Authentication ServerEnd-to-End Encrypted Cloud Keychain SyncUNIX / Linux / Windows Operating System KernelHardware Memory Management Unit (MMU)CPU Advanced Programmable Interrupt Controller (APIC)Kernel Virtual File System (VFS) & Process SchedulerIdentity Provider (IdP) Authorization Server (Google, Okta, Microsoft Entra ID)Relying Party / Client Application (Web / Mobile App Backend)User-Agent (Web Browser / Native OS Webview)Resource Server (Protected API Endpoints)First-Stage Retrieval Shards (Inverted Index / Vector HNSW)LightGBM / XGBoost Second-Stage Scoring ClustersDeep Transformer Inference Accelerators (TPU / GPU)Search Engine Result Page (SERP) Aggregator & Layout EngineComplementary Metal-Oxide-Semiconductor (CMOS) LogicSilicon Gate Field-Effect Transistor FabricStatic Digital Voltage Margin ArchitectureMicroprocessor Arithmetic Logic Unit (ALU)High-Speed Binary Parallel Prefix TreeProcessor Status Register & Condition Code FlagsMicroprocessor Clock Generation & Distribution NetworkPhase-Locked Loop (PLL) Frequency SynthesizerSynchronous Register-Transfer-Level (RTL) DatapathHierarchical Microprocessor Cache Subsystem (L1, L2, L3)Multicore Interconnect Fabric (Ring Bus / 2D Mesh)Hardware Cache Coherency Controller3D Vertical NAND (V-NAND) Charge-Trap Memory ArrayMulti-Core NVMe SSD Controller & DRAM Mapping CacheFlash Translation Layer (FTL) & Low-Density Parity-Check (LDPC) ECC EngineLLVM Compiler Infrastructure (Clang Frontend & LLVM Backend)GNU Compiler Collection (GCC)System V AMD64 Application Binary InterfaceOperating System Dynamic Linker (ld-linux.so / dyld)MIPS / RISC-V 5-Stage Datapath ArchitectureInterstage Pipeline Latch Register BusBranch Target Buffer & History Table (BTB/BHT)Database Storage Engine & In-Memory Page Buffer PoolSequential Write-Ahead Log (WAL) Ring Buffer & Disk Sync SubsystemLock Manager, Hash Table & Transaction Concurrency ControllerARIES Crash Recovery Engine & Checkpointing Daemonx86-64 Four-Level Hierarchical Paging ArchitectureCPU Hardware Memory Management Unit (MMU)Translation Lookaside Buffer (TLB) Hardware CacheOperating System Virtual Memory Subsystem (Linux mm)Hardware Page Fault Exception Handling VectorQuantum Processing Unit (QPU)Dilution Refrigerator (15 mK Cryostat)Superconducting Transmon QubitsTrapped-Ion Qubit ArrayArbitrary Waveform Generator (AWG) Control RackFIPS 140-2 / 140-3 Level 3 & Level 4 Physical Cryptographic EnvelopesPCI PTS Hardware Security Modules (Payment HSMs: Thales payShield, Atos, Futurex)General Purpose HSMs (Luna, nCipher, AWS CloudHSM, Google Cloud CloudHSM)PKCS#11 Cryptographic Token Interface and Microsoft CAPI/CNG
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