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ComputingTopic Knowledge Hub

Computing & Digital Architecture

From mechanical calculation to modern digital computers: binary logic, CPU instruction cycles, memory hierarchies, and operating systems.

17 Published Explainers
59 Systems Analyzed
134 Core Concepts
2 Inquiry Path
Recommended Starting Point

How AI Agents Work

The architectural loop behind autonomous planning, tool execution, and stateful problem solving

Core Question Answered
“What actually happens behind the scenes when an AI agent solves a problem on its own?”
Agent RuntimeReAct PatternFunction CallingWorking Memory Context
Read Explainer

Inquiry Learning Paths

Structured sequences designed to take you from foundational mechanics to complex interactions.

From Next-Token Prediction to Autonomous AI Agents

A step-by-step inquiry path tracing how statistical word prediction scales into goal-directed agents that use tools in the real world.

1

How Large Language Models Generate Text

Foundational mechanism: Next-token autoregressive generation

2

Why AI Chatbots Sometimes Make Things Up

Failure mode: Statistical plausibility vs. factual grounding

3

How AI Agents Work

Autonomous architecture: Closing the ReAct tool execution loop

4

How an AI Agent Decides Which Tool to Use

Decision layer: Schema matching and constrained token decoding

Authentication, Cryptographic Clocks & Carrier Signals

Why local mathematical time drift protects your accounts when telecommunication signaling networks delay text messages.

1

How OTP and Two-Factor Authentication Actually Work

Local mathematics: Synchronized Unix timestamps and HMAC secret verification

2

Why SMS OTPs Sometimes Arrive Late or Fail Entirely

Telecom physics: Store-and-forward SMS queues and SS7 carrier chokepoints

All Published Explainers

Every verified first-principles analysis in this domain.

Explainer

How AI Agents Work

The architectural loop behind autonomous planning, tool execution, and stateful problem solving

First-Principles ExplainerRead
Explainer

How Large Language Models Generate Text

From raw prompt strings to token embeddings, self-attention calculations, and next-token probability sampling

First-Principles ExplainerRead
Explainer

How OTP and Two-Factor Authentication Actually Work

From shared cryptographic secrets and Unix timestamps to dynamic truncation and SMS delivery risks

First-Principles ExplainerRead
Explainer

How Search Engines Actually Work

Web crawling, inverted indexing, PageRank link graphs, and neural vector retrieval across 50 billion pages

First-Principles ExplainerRead
Explainer

How Binary and Logic Gates Became Computation

How George Boole mapped human thought to two numbers, Claude Shannon proved switches could do algebra, and silicon transistors turned electric currents into logic

First-Principles ExplainerRead
Explainer

How an AI Agent Decides Which Tool to Use

The mechanics of schema matching, token probabilities, and semantic tool routing

First-Principles ExplainerRead
Explainer

Why AI Chatbots Sometimes Make Things Up

The mechanics of hallucination, probability vs. truth, and the engineering behind grounded AI responses

First-Principles ExplainerRead
Explainer

Why SMS OTPs Sometimes Arrive Late or Fail Entirely

The multi-hop journey from enterprise application servers through telecommunication aggregators, SMPP queues, and cellular signaling networks

First-Principles ExplainerRead
Explainer

Why Search Results Differ Between People

Geographic IP Anycast routing, session history vectors, freshness ranking, and A/B experiment flight allocation

First-Principles ExplainerRead
Explainer

How a CPU Executes an Instruction

The microscopic journey of a clock tick: how registers, program counters, instruction decoders, and arithmetic units turn memory bytes into physical computation

First-Principles ExplainerRead
Explainer

How Public-Key Cryptography Actually Works

One-way mathematical trapdoors, modular clock arithmetic, Diffie-Hellman key exchange, and the RSA prime factor breakthrough

First-Principles ExplainerRead
Explainer

How Computer Memory (RAM) Actually Works

Capacitor charge leakage, 1T1C bit cells, differential sense amplifiers, and the nanosecond choreography of DRAM refresh

First-Principles ExplainerRead
Explainer

How an Operating System Actually Runs Software

Hardware privilege rings, preemptive timer interrupts, MMU virtual memory page tables, and context switching

First-Principles ExplainerRead
Explainer

How CMOS Transistors Form Logic Gates

Complementary NMOS and PMOS pairs, silicon pull-up and pull-down networks, voltage transfer margins, and the physical mechanics of Boolean switches

First-Principles ExplainerRead
Explainer

How Binary Arithmetic Logic Units Actually Add Numbers

From half adders and ripple-carry latency to carry-lookahead prefix trees, two's complement subtraction, and status flag generation in physical silicon

First-Principles ExplainerRead
Explainer

How the CPU Clock Synchronizes Billions of Transistors

Quartz piezoelectric vibration, phase-locked loop multiplication, H-tree distribution grids, clock skew, and setup-and-hold timing margins

First-Principles ExplainerRead
Explainer

How CPU Cache Hierarchies Overcome the Memory Wall

6T SRAM bistable latches, spatial and temporal locality, set-associative tag matching, and MESI multicore cache coherency

First-Principles ExplainerRead

Inquiry Roadmap & Research Pipeline

Next-order causal questions in this discipline currently undergoing source verification and mechanism synthesis.

2 Queued Inquiries
Upcoming InquirySource Verification

“How Logic Gates Become a CPU”

Trace the architectural progression from semiconductor switching behaviors to complete microprocessors, analyzing combinatorial logic, arithmetic-logic units, sequential registers, and the control state machine driving instruction execution.

transistor switch logichalf adder and full adderarithmetic logic unit ALU
Upcoming InquirySource Verification

“How Operating Systems Were Invented”

Investigate the historical evolution of system software, analyzing how the constraints of early batch processing and hardware contention motivated supervisory programs, hardware interrupts, process scheduling, and virtual memory.

batch processing monitorsmultitasking and time-sharinghardware abstraction layer

Technical Systems & Protocols Analyzed

Hardware, protocol switches, and central clearing houses examined in this hub.

Large Language ModelSandbox EnvironmentTool API GatewayTransformer Neural NetworkTokenizer BPE EngineInference Server (KV Cache)Authenticator AppAuthentication ServerSMS GatewayDistributed Web Crawlers (Googlebot)Inverted Index ShardsDocument Forward IndexLink Graph EngineServing Cache & Query AggregatorCross-Encoder Neural Re-rankerLeibniz Binary Notation SystemShannon Relay-Switching NetworkCMOS Logic Gate ArchitectureArithmetic Logic Unit (ALU) Adder CircuitFunction RegistrySemantic RouterVector DatabaseRAG PipelineRLHF Reward ModelGlobal Telecom Signaling Network (SS7/Diameter)Carrier SMSCDistributed Ledger Technology (DLT) GatewayGeolocation Edge ResolverShort-Term Session Memory StoreReal-Time Freshness Ingestion StreamExperimentation & Traffic Splitting FrameworkMobile-First Rendering PipelineVon Neumann Computer ArchitectureClassic 5-Stage RISC Instruction PipelineMicroprocessor Register File & Internal Bus SystemL1/L2 High-Speed CPU Cache HierarchyTransport Layer Security (TLS 1.3 / HTTPS)Public Key Infrastructure (PKI) & Certificate AuthoritiesSSH Secure Shell Key AuthenticationFIDO2 / WebAuthn Passkey Cryptographic Token InfrastructureDDR4 / DDR5 Synchronous Dynamic RAM ArchitectureMemory Controller Hub (Integrated Memory Controller - IMC)Physical Memory Bus & Double Data Rate (DDR) SignalingUNIX / Linux / Windows Operating System KernelHardware Memory Management Unit (MMU)CPU Advanced Programmable Interrupt Controller (APIC)Kernel Virtual File System (VFS) & Process SchedulerComplementary Metal-Oxide-Semiconductor (CMOS) LogicSilicon Gate Field-Effect Transistor FabricStatic Digital Voltage Margin ArchitectureMicroprocessor Arithmetic Logic Unit (ALU)High-Speed Binary Parallel Prefix TreeProcessor Status Register & Condition Code FlagsMicroprocessor Clock Generation & Distribution NetworkPhase-Locked Loop (PLL) Frequency SynthesizerSynchronous Register-Transfer-Level (RTL) DatapathHierarchical Microprocessor Cache Subsystem (L1, L2, L3)Multicore Interconnect Fabric (Ring Bus / 2D Mesh)Hardware Cache Coherency Controller
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